The current trend for developing electronic products is heading towards fabricating a device with a minimized and compact size, improved functions, and increased input/output connections. Typically, a conventional semiconductor package is fabricated by packaging a single integrated circuit (IC) or semiconductor chip with a lead frame or substrate via processes such as die attach, wire bonding, molding, and trim and form processes, making the size of the fabricated package be several times of that of the semiconductor chip. A later developed flip-chip technology involves forming gold (Au), tin/lead (Sn/Pb) or other metal bumps on the semiconductor chip, allowing the metal bumps to be soldered to solder pads on a flip-chip substrate. The current flip-chip technology has been improved in a manner that a package can be made having a size almost the same as that of the chip, and such package is customarily referred to as Chip Scale Package (CSP). The flip-chip technology provides significant benefits, such as high density, low induction, easy control over high frequency noise, minimized package size, and so on, thus fulfilling the packaging requirements for the above-mentioned highly efficient and portable products in the future.
Although the flip-chip semiconductor package has the above benefits, it is still necessary to further improve the current packaging technology in terms of downsizing the device in response to the semiconductor fabrication process developed towards a finer pitch arrangement. Referring to FIG. 1a showing a conventional flip-chip semiconductor chip carrier 1, a plurality of solder pads 11 are formed on predetermined positions of a substrate 10, for allowing a plurality of metal bumps on a semiconductor chip (not shown) to be soldered to the solder pads 11 on the substrate 10. A typical pitch between the adjacent solder pads is limited to the size of about 200 to 250 μm according to the current substrate manufacturing capacity. However, for a flip-chip package having a chip formed with solder pads at its peripheral positions, the pitch between metal bumps on the chip is always sized smaller than 150 μm. Therefore, in such flip-chip package, as shown in FIG. 1b disclosed in U.S. Pat. No. 6,404,064, solder pads 11′ on a substrate 10′ are formed by grooves 13 in a solder mask layer 12 on the substrate 10′ so as to achieve a pitch sized smaller than 150 μm between the adjacent solder pads 11′.
Although the above-mentioned technique can solve the problem of reducing the pitch between the adjacent solder pads, other serious problems are incurred as a result of variously sized pitches between the solder pads. Referring to FIG. 1c, there are at least formed a pitch A and a pitch B between the adjacent solder pads 11″, wherein the pitch A is sized smaller than the pitch B. As shown in FIG. 1d, once a semiconductor chip 17 is mounted on the substrate 10′ in a flip-chip manner and a reflow process is performed for soldering the metal bumps on the chip 17 to the solder pads 11′ on the substrate 10′, then an underfill process is carried out to fill a gap between the chip 17 and the substrate 10′ with an underfill resin 14. Since the underfill resin 14 flows faster through the relatively wider pitch B than the relatively narrower pitch A, voids 15 would be formed by air trapped in the relatively narrower pitch A as shown in FIG. 1e. Subsequently, as shown in FIG. 1f, an undesirable bridging effect between the metal bumps may be caused by the voids 15 between the adjacent metal bumps 16 during subsequent reflow and surface-mount technology (SMT) processes, thereby reducing the package yield.
Therefore, the problem to be solved here is to provide a chip carrier with bumps pads being arranged in differently sized pitches so as to prevent formation of voids due to differently sized pitches between the solder pads during an underfill process.